1. Field of the Invention
The present invention relates to semiconductor memories and, in more particular, to non-volatile semiconductor memories having NAND type memory cell units which are programmable and which may be electrically erased.
2. Description of the Related Art
With the increasing needs for high performance and reliability of digital computer systems, the technique for highly integrated memory cells becomes indispensable. A solid-state memory with enhanced data storage capability has been demanded strongly, which can replace existing external data storage devices for digital computer systems, such as a magnetic floppy diskette drive unit, a fixed disk unit, or the like.
A presently available electrically erasable programmable read-only memory (to be referred to as an "EEPROM" hereinafter) has technical advantages, such as being superior in reliability and higher in data programming rate than the magnetic data storage devices are; however, the total memory amount of the EEPROM is still not so large as to replace the magnetic data storage devices. In the EEPROM, since each of the memory cells is generally constituted by two transistors, it cannot be expected that the integration density increases enough to be sufficient to enable the EEPROM to have a required amount of memory that permits the EEPROM to substitute for the known magnetic data storage devices.
Recently, a "NAND" type EEPROM has been developed as one of non-volatile semiconductor memories with enhanced storage capability. According to the memory of this type, memory cells are grouped into a preselected number of memory cell block sections, each of which includes a plurality of arrays of memory cells, what are called "NAND" cell arrays, or "NAND" cell units. Every one of the memory cells constituting the "NAND" cell unit typically consists of only one transistor of floating gate type, so that only one contact portion is required between every array of memory cells and the corresponding bit line associated therewith. The occupied area of the overall memory cell section on the substrate can thus be reduced to be much smaller than that of a conventional EEPROM, whereby the integration density of the EEPROM can be improved, with the result in the total amount of memory being increased.
According to the NAND type EEPROM, data may be written into, read from, or erased in a desired memory cell transistor by transferring by tunneling between the floating gate of the transistor and the substrate through an insulative thin-film formed therebetween. In this sense, this type of memory cell is also known as the "FETMOS" type memory cell.
More specifically, if the memory cell is an N-channel type transistor, electrons can be injected by tunneling from the drain region into the floating gate thereof by applying a high-level voltage such as 20 volts to the control gate of the cell transistor, while its drain layer is being set to 0 volts. As a result, the threshold value of the cell transistor is level-shifted in the positive polarity direction.
In order to "release" the electrons stored in the floating gate to the substrate, a high-level voltage of 20 volts, for example, is applied to the drain region of the cell transistor, with the control gate thereof being set to 0 volts. The threshold value of the transistor, in this case, is level-shifted along the negative polarity direction. The data writing and erasing operations in the cell transistor may be performed using these two different kinds of voltage applications.
To read the data stored in the cell transistor, a read voltage having a preselected potential level is applied to the control gate of the transistor. The logical "type" of stored data, i.e., logical "0" or "1," can be determined by detecting or sensing whether or not channel-current flows in the transistor under such voltage application.
The NAND type EEPROM highly integrated, however, suffers from undesirable occurrence of the "breakdown" phenomenon, as will be explained hereinafter. When the high-level voltage is applied to the drain region of a memory cell transistor during the data write and erase modes, the breakdown will occur in the PN junction, e.g., between the drain region and a channel-stopper layer formed in adjacent thereto in the substrate. Such breakdown will also occur in the surface portion of the drain region: it is generally known as the "surface breakdown."
The breakdown is very serious for the EEPROM because it damages greatly the performance of data write/erase operations. Even if it is not a "complete" breakdown, i.e., if a partial breakdown occurs, current flow in the substrate abnormally increases, which makes it difficult or impossible to successively "remove" from the floating gate the electrons being stored or accumulated therein. Difficulty in the removal of stored electrons will lead to decrease in the operating reliability of the EEPROM, or to malfunction thereof in the worst case. The same is true in the case of an EEPROM with what is called "FLOTOX" type memory cells, or of an "ultraviolet ray-erase" type EPROM.